Flash Profiling

This project is intended to explore the characteristics of the storage devices based in flash technology. The idea is to get a better understanding of the internals in this type of memory and create a model which allow a more effective use of these drives. To complete this task, we will create techniques that characterize the flash devices automatically. We will profile different devices, mostly SSDs, ranging from mobile- to enterprise-intended, SATA to PCI-e interfaces and sizes of 16GB to 70GB approximately.

• 10/06/09: Paper structure discussion
• 09/08/09: Write execution model discussion
• 09/01/09: Motivating the model (initial discussion)
• 08/25/09: Paper message and structure discussion
• 08/20/09: Write execution path and Hypotheses discussion
• 08/17/09: Hypothesis discussion, Paper Structure and Message
• 08/06/09: Read execution path finalized, simulator initial steps
• 07/27/09: Operation wait exeuction path + unfrag/frag state reads
• 07/23/09: New experiments – reverse sequential write, mixed, frag/unfragmented
• 07/20/09: MASCOTS'09 profiling rejected paper discussion
• 07/16/09: Refining read execution path and analyzing new graphs
• 07/13/09: New paper draft and read execution path discussions
• 07/09/09: Reviewing list of SSD design parameters affecting performance
• 07/06/09: Reviewing continued and plan for modified paper direction
• 07/02/09: Reviewing Sigmetrics09 flash characterization paper
• 06/29/09: Reviewing all experiments to date
• 06/25/09: Sequential writes and modeling plan
• 06/22/09: Discussing new experiments with sequential writes w/ and w/o throttling
• 06/15/09: Alternative modeling options for write performance
• 06/09/09: Update on progress
• 04/29/09: One month plan and Sigmetrics paper discussion
• 04/07/09: Write Modeling and Initial Graphs
• 04/03/09: Modeling write latency
• 03/24/09: Write experiments discussion
• 03/20/09: Resolving write I/O issuing problem and some write modeling discussion
• 03/10/09: Modeling writes - some problems with profiling experiments
• 03/03/09: Modeling write latency and cleaning - graphs from Luis (not d2c)
• 02/17/09: Discussion about write profiling and SSD simulator
• 02/10/09: SSD Simulator experiments update
• 02/03/09: Logical simulator discussion
• 01/26/09: Using hardware simulator, logical vs. physical model, paper writing
• 01/09/09: Pre-UTC deadline discussion – plans for next submission
• 01/07/09: First full model discussion
• 01/05/09: Evening session: Explaning SanDisk Read graph
• 01/05/09: Afternoon session: paper discussion and task-list
• 01/02/09: Important discussion finally explaining the graphs and model refinement to incorporate this
• 12/31/08: UTC paper model discussion, layout, and applications
• 12/16/08: UTC paper motivation, layout, and experiments presentation
• 11/24/08: (Evening): Paper contents discussion and modeling read response times
• 11/24/08: (Afternoon): Analyzing read response time graphs
• 11/10/08: Discussion of read/write graphs and time-line experiments
• 10/27/08: Discussion on block size experiments and older pattern-size reads - in 2 parts
• 10/21/08: New flash-scheduler brainstorming and Block-size profiling discussion

We are starting a fresh wiki-page with new experiments and results. The old wiki page can be found in old_start.

Complete date of the most recent experiments can be found in the http://apu.cs.fiu.edu/~luis/flash/. It is recommended to read http://apu.cs.fiu.edu/~luis/flash/README.txt before using the data.